1. Field of the Invention
The present invention relates generally to the field of semiconductor components and more specifically to the field of integrated circuits. It more particularly relates to the structure and manufacturing of multiple layer connection networks formed on such components.
2. Discussion of the Related Art
An integrated circuit formed on a silicon chip includes various regions with different types of dopings, for example corresponding to drains, sources and gates of MOS transistors. Contacts have to be made on these regions, some of the regions must be interconnected, and access must be provided to output terminals. To solve the interconnect and connection crossing problems, several levels of interconnects have to be made. These interconnect levels are currently called metallizations. It should be noted that the conductive connection components are not always metals but can also be formed from several other conductive materials. In the following description, the expression "metallization level" designates a conductive layer formed at a given stage and etched appropriately. The expression "via" designates a path formed in a insulating layer between two metallization levels and filled with a conductive material to enable localized connections between portions of two separate metallization levels.
Several structures and methods used to construct these metallization layers and vias are known. However, there is a constant need for improvement of these structures and methods due to the increasing miniaturization of integrated circuits. Presently, elementary dimensions lower than 1 .mu.m are reached. Clearly, structures and methods developed for constructing structures in which the minimal dimensions were higher than one micrometer are no longer adequate and therefore new methods have to be developed. The alterations can sometimes appear to be very slight, but they are of major importance in that they make possible what used to be impossible.
Besides the various problems associated with the proper filling of the vias and the compatibility between materials, the size reduction of integrated circuits particularly increases the acuteness of two particular problems. The first problem lies in the fact that, for large circuits, the stray lateral capacitances between metallization levels dominate the lateral capacitances between portions of a same metallization level, whereas the relationship tends to reverse as the miniaturization increases. The second problem arises because as the miniaturization increases, the number of components formed in a same silicon chip increases and thus the number of connections increases correlatively. As a result, the resistance of the interconnects, the vias and the interconnect/via interfaces becomes a critical problem, in particular when it is desired to have the integrated circuit operate at high frequencies.